MANUFACTURING DESCRIPTION

Manufacturer's JEDEC ID Code:

MSC Vertriebs GmbH

Module Manufacturing Location:

01h

Module Part Number:

CS2221440

Module Revision Code:

0100h

Module Manufacturing Date:

Week 46, 2006

Module Serial Number:

00019734h

LEGITIMATE ARCHITECTURES

Fundamental Memory Type:

DDR2 SDRAM

DIMM configuration type:

Non-ECC/Parity

DIMM type information:

UDIMM (133.35 mm)

Number of Row Addresses:

14

Number of Column Addresses:

10

Number of Ranks:

2

Module Rank Density:

512 MB

Number of Banks on SDRAM Device:

4

Module Data Width:

64 bits

Primary SDRAM Width:

x8

Error Checking SDRAM Width:

N/A

Voltage Interface Level:

SSTL 1.8 V

Refresh Rate/Type:

7.8 us Self Refresh

DDR SDRAM DIMM Height:

30.0 mm

TIMING SPECIFICATIONS

Burst Lengths Supported:

4, 8

CAS# Latencies Supported (tCL):

3T, 4T, 5T

Cycle time at Max CAS Latency:

2.5 ns

SDRAM Access from Clock (tAC):

0.40 ns

Minimum Clock Cycle at tCL = X - 1:

3.13 ns

Max Data Access Time at tCL = X - 1 (tAC):

0.40 ns

Minimum Clock Cycle at tCL = X - 2:

5.0 ns

Max Data Access Time at CL = X - 2 (tAC):

0.40 ns

Minimum Active to Precharge Time (tRAS):

45.0 ns

Minimum RAS to CAS delay (tRCD):

12.50 ns

Minimum Row Precharge Time (tRP):

12.50 ns

Min Active to Active/Auto Refresh Time (tRC):

55.0 ns

Min Auto Ref to Active/Auto Refresh (tRFC):

105.0 ns

Min Row Active to Row Active delay (tRRD):

7.50 ns

Write Recovery Time (tWR):

15.0 ns

Internal write to read command delay (tWTR):

7.50 ns

Internal read to precharge command delay (tRTP):

7.50 ns

Addr and CMD Input Setup Time Before Clock (tIS):

0.17 ns

Addr and CMD Input Hold Time After Clock (tIH):

0.25 ns

Data Input Setup Time Before Clock (tDS):

0.05 ns

Data Input Hold Time After Clock (tDH):

0.12 ns

Device Max device cycle time (tCKmax):

8.0 ns

Max skew between DQS and DQ signals (tDQSQ):

0.20 ns

Max Read Data Hold Skew Factor (tHQS):

0.24 ns

SPD PROTOCOL

Number of bytes written into SPD:

128

Total number of bytes of SPD:

256

SPD Revision:

1.2

Checksum for Bytes 0-62:

F6h

SUMMARY SPECIFICATION

Module Type: DDR2 SDRAM PC2-6400 (DDR2-800)

Module Size: 1024 MB

Frequency	tCL	tRCD	tRP	tRAS	tRC	tRFC	tRRD	tWR	tWTR	tRTP
400 MHz	5.0	5	5	18	22	42	3	6	3	3
267 MHz	4.0	4	4	12	15	28	2	4	2	2
200 MHz	3.0	3	3	9	11	21	2	3	2	2