MANUFACTURING DESCRIPTION

Manufacturer’s JEDEC ID Code:

G-Skill Intl

Module Manufacturing Location:

54h

Module Part Number:

CL3-4-4-8-Gskill

Module Revision Code:

0000h

Module Manufacturing Date:

Week 2, 2004

Module Serial Number:

00000000h

LEGITIMATE ARCHITECTURES

Fundamental Memory Type:

DDR SDRAM

DIMM configuration type:

Non-ECC/Parity

Number of Row Addresses:

13

Number of Column Addresses:

10

Number of DIMM Banks:

2

Module Bank Density:

256 MB

Number of Banks on SDRAM Device:

4

Module Data Width:

64 bits

Primary SDRAM Width:

x8

Error Checking SDRAM Width:

N/A

Voltage Interface Level:

SSTL 2.5V

Refresh Rate/Type:

7.8 us Self Refresh

DDR SDRAM DIMM Height:

N/A

TIMING SPECIFICATIONS

Burst Lengths Supported:

2, 4, 8

CAS# Latencies Supported (tCL):

3T, 2.5T

CS# Latency:

0T

WE# Latency (Write Delay):

1T

Cycle time at Max CAS Latency:

3.6 ns

SDRAM Access from Clock (tAC):

0.65 ns

Minimum Clock Cycle at tCL = X - 0.5:

5.0 ns

Max Data Access Time at tCL = X - 0.5 (tAC):

0.70 ns

Minimum Clock Cycle at tCL = X - 1:

0.0 ns

Max Data Access Time at CL = X - 1 (tAC):

0.00 ns

Minimum Active to Precharge Time (tRAS):

40.0 ns

Minimum RAS to CAS delay (tRCD):

20.0 ns

Minimum Row Precharge Time (tRP):

20.0 ns

Min Active to Active/Auto Refresh Time (tRC):

55.0 ns

Min Auto Ref to Active/Auto Refresh (tRFC):

70.0 ns

Min Row Active to Row Active delay (tRRD):

10.0 ns

Addr and CMD Input Setup Time Before Clock:

0.60 ns

Addr and CMD Input Hold Time After Clock:

0.60 ns

Data Input Setup Time Before Clock:

0.40 ns

Data Input Hold Time After Clock:

0.40 ns

Device Max device cycle time (tCKmax):

10.0 ns

Max skew between DQS and DQ signals:

0.40 ns

Max Read Data Hold Skew Factor:

0.50 ns

Back-to-Back Random Col Access (tCCD):

1T

SPD PROTOCOL

Number of bytes written into SPD:

128

Total number of bytes of SPD:

256

SPD Revision:

0.0

Checksum for Bytes 0-62:

6Ch

SUMMARY SPECIFICATION

Module Type: DDR SDRAM PC4448 (DDR556)

Module Size: 512 MB

Frequency	tCL	tRCD	tRP	tRAS	tRC	tRFC	tRRD
278 MHz	3.0	6	6	12	16	20	3
200 MHz	2.5	4	4	8	11	14	2